Semiconductor dice (also referred to as chips/dice herein) are found in many electronic products today. As semiconductor dice get smaller and more complex, the problem of making electrical connections between semiconductor dice and carrier substrates such as printed circuit boards or intermediate substrates, has been addressed with a variety of constantly evolving solutions.
One of the earlier solutions included wire bonding from signal connection devices such as bond pads, of a semiconductor die, to pins or leads of a lead frame contained in a ceramic or plastic package. Finished packages were mounted to a carrier substrate such as a printed circuit board, where the pins or leads made electrical connection with contact structures of the carrier substrate.
The use of wires for connecting a semiconductor die to a substrate and the wire bonding processes in particular, are problematic. Problems include, for example: tight size and pitch (spacing) requirements for the bond pads of the semiconductor die and contact pads of the substrate; inductance in the signals due to the long curved wires; wire bond breakage and wire sweep causing shorting between adjacent wires; and, high signal frequency semiconductor dice making the wire bonding process difficult and expensive. These problems became more pronounced as levels of integration increase and as each semiconductor die is manufactured to include increasingly more signal connection devices, such as bond pads and the like.
Flip-chip technologies using solder balls or bumps have helped to alleviate some of these problems. In flip-chip packaging, instead of wire bonding, conductive bumps such as balls of solder, may be formed at the locations of the bond pads of a semiconductor die. A lead frame with a package substrate having contact pads corresponding to the bumps, is also formed. Alternatively, other carrier substrates such as a printed wiring board may have electrical connection locations such as terminals which correspond to the placement of the solder balls on the bond pads of the semiconductor die. In assembly, the semiconductor die is “flipped” upside down so the solder balls are placed, for example, on the corresponding contact pads of the package substrate.
This packaging solution alleviates at least some of the inductance problems, allowing for higher frequency performance and better signal integrity of the semiconductor die. Also, to a certain extent, it allows the contact pads of a substrate to be larger, more widely pitched and placed anywhere on the semiconductor die active surface rather than just around the periphery or down the center thereof.
The assembly process consists of joining the solder bumps of the die to the contact pads on the package substrate. A solder reflow process heats the solder balls until the solder begins to flow and bond with the corresponding contact pad. Prior to being joined and heated, a flux is applied to at least one of the surfaces to be joined to assist in the solder/reflow processes by isolating the surface from the atmosphere and providing an adhesive force to hold the die to the substrate during the process. Upon cooling, the solder forms both mechanical and electrical connections between the carrier substrate and the semiconductor die and the flux must then be removed by a subsequent cleaning procedure. For example, a wash and bake cycle may be used to remove the flux.
An epoxy under-fill is applied between the active surface of the chip and the facing surface of the substrate to surround and support the solder interconnects. Under-filling significantly increases the reliability and fatigue resistance of the package interconnections. The under-fill helps to more evenly distribute stress caused by thermally induced strains due to the differences in coefficients of thermal expansion (CTE) between the chip and substrate, across the entire surface of the chip and substrate. If the gap between the interconnected die and substrate were not under-filled, the stress would be carried by the relatively thin solder interconnects, often resulting in premature package failure. However, in order for the under-fill to perform properly, it must be well adhered to the die and substrate surfaces. Even a thin film of flux residue can cause premature delamination of a bonded surface, eventually resulting in failure in one or more of the interconnects. Accordingly, it is critical to completely remove all flux residues from the package. This has become even more challenging as the thickness of the gap between the die and the substrate has decreased.
Moreover, semiconductor die now have increased numbers of bond pads formed in closer proximity as integration levels increase. As a result, there are more bumps formed in close proximity on the semiconductor die. Since the bump pitch is becoming increasingly smaller, the assembly process becomes more difficult and creates more reliability issues such as the aforementioned incomplete flux cleaning. In addition to causing delamination of the underfill around the bump region, flux residue can cause shorting between respective bumps and other reliability issues and therefore the removal of the residual flux is especially critical. It would be desirable to provide a bump pattern that accommodates the high density demands of the advancing semiconductor manufacturing industry and alleviates reliability problems such as associated with residual flux in an efficient and cost-effective manner.